Parallelism and Concurrency

Memory consistency models (MCM) specify the order in which memory accesses performed by one processor become visible to other processors. Sequential Consistency (SC) is a strong and intuitive memory model that requires the memory accesses of a program appear to have been executed in a global sequential order consistent with the per-processor program order. We use atomic block as a key structure to support SC from application to architecture. An atomic block is a contiguous of instructions that are executed atomically and in isolation. It can be used as a mechanism to implement SC in architecture and as an interface that the software/compiler can use to demarcate the transformed codes that need to be executed atomically, making sure that SC is not violated by the software/compiler. We proposed several coherence protocols [ScalableBulk (MICRO'10)][BulkCommit (MICRO'13)][OmniOrder (ISCA'14)][BulkSMT (HPCA'12)] designed for continuous atomic block execution. For relaxed MCM, we proposed the architectural debugging supports [Volition (ASPLOS'13)][Rainbow (HPCA'13)][Pacifier (ISCA'14)] that detect SCVs and record data races for deterministic record and replay.